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222 ps8315-2 04/08/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c103 precision clock synthesizer for mobile pcs pciclk_f pciclk1 xtal_out pciclk2 pciclk3 v ss v dd pciclk4 pciclk5 v dd 48 mhz 48-24mhz/ts# v dd ref0/spread# v dd 2 cpuclk1 v ss 2 v ss pci_stop# v dd cpu_stop# pwr_dwn# sel100/66# v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v ss xtal_in cpuclk0 ref1/sel48# pin configuration block diagram description the pi6c103 is a high-speed, low-noise clock generator designed to work with the pi6c18x clock buffer to meet all clock needs for mobile intel architecture platforms. system clock frequencies of 66.6 mhz and 100 mhz are supported. split supplies of 3.3v and 2.5v are used. the 3.3v power supply powers everything except the cpu clock. the 2.5v power supply is used to power the cpuclk outputs. 2.5v signaling follows jedec standard 8-x. power sequencing of the 3.3v and 2.5v supplies is not required. an asynchronous pwr_dwn# signal may be used to orderly power down (or up) the system. cpu and pci clocks may also be stopped by the cpu_stop# and pci_stop# signals. the pi6c103 contains the spread spectrum function for only those clocks that synchronize to the cpu clocks (cpu and pci clocks). 28-pin h, l features ? two copies of cpu clock ? 100 mhz or 66.6 mhz operation ? six copies of pci clock, (synchronous with cpu clock) ? two copies of ref clock @ 14.31818 mhz ? one copy of 48 mhz ? one copy of selectable 48/24 mhz ? power management control input pins ? isolated core v dd , v ss pins for noise reduction ? 28-pin ssop (h) and tssop (l) packages ref [0:1] pciclk [1:5] cpuclk [0:1] ref osc cpu_stop# 2 2 5 pciclk_f 48 mhz 48/24 mhz pci_stop# div 2 pll1 xtal_out xtal_in sel100/66# sel48# spread# pwr_dwn# mux pll2 ts# ? ssc options: device 66 mhz 100 mhz pi6c103 ?0.67% ?0.65% pi6c103-05 ?1.35% ?1.35% pi6c103-06 ?1.79% ?1.79%
223 ps8315-2 04/08/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c103 precision clock synthesizer for mobile pcs pin description notes: 1. v dd and v ss names in the above table reflect a likely internal power and ground partition to reduce the effects of internal noise on the p erformance of the device. in reality, the platform will be configured with the same voltage v dd pins tied to a common supply and all v ss pins being common. the v dd /v ss naming convention above is done to show how the pinout is dominated by the need to isolate all the signals. 2. the output frequency at this pin is dependent on the power on strapping option at pin 27. a 48 mhz output when power-on strap ped low, and 24 mhz output when strapped high. this pin also serves as hi-z state strapping option during power-on configuration. during power-on, the pi6c103 will sample the value at this pin. strapped low for hi-z state mode and high for normal operation. 3. this is a dual function pin. during power-on, all clock outputs are disabled, and the pi6c103 will sample the spread spectrum enable/disable strapping option. after the strapped value latches, all clock outputs will be enabled simultaneously and this pin will become a 14.318 mh z reference clock output. the power-on latency needs to be less than 3ms after the supply voltage stabilized. 4. this is a dual function pin. during power-on, all clocks are disabled, and pi6c103 will sample the sel48# strapping option. a fter the strapped value latches, all clock outputs will be enabled simultaneously and this pin will become another 14.318 mhz reference clock out put. the power- on latency needs to be less than 3ms after the supply voltage stabilized. 5. internally pulled up with resistor min.value of 50k w . e g a k c a p n i p - 8 2 e p y tl o b m y sn o i t p i r c s e d n i p. y t q 21t u p n in i _ l a t xt u p n i l a t s y r c z h m 8 1 3 . 4 1 31 t u p t u ot u o _ l a t xz h m 8 1 3 . 4 1t u p t u o l a t s y r c 41 t u p t u of _ k l c i c pt u p t u o k c o l c i c p g n i n n u r e e r f v 3 . 3 1 1 , 0 1 , 9 , 6 , 55t u p t u o] 5 - 1 [ k l c i c ps t u p t u o k c o l c i c p v 3 . 3 3 11t u p t u oz h m 8 4t u p t u o k c o l c z h m 8 4 v 3 . 3 4 11t u p t u o# s t / z h m 4 2 - 8 4 d n a t u p t u o z h m 4 2 r o 8 4 v 3 . 3z - i hn o i t p o g n i p p a r t s e t a t s ) 5 , 2 ( r e t n e = w o l p a r t sz - i hn o i t a r e p o l a m r o n = h g i h p a r t s , g n i t s e t r o f e d o m e t a t s 6 11t u p n i# 6 6 / 0 0 1 l e s k c o l c u p c z h m 6 6 r o z h m 0 0 1 g n i l b a n e r o f t c e l e s ) 5 ( z h m 6 6 = l , z h m 0 0 1 = h 7 11t u p n i# n w d _ r w p5 w o l n e h w e d o m n w o d r e w o p s r e t n e e c i v e d 8 11t u p n i# p o t s _ u p ce t a t s w o l n i s k c o l c u p c p o t s , w o l n e h w 0 21t u p n i# p o t s _ i c p t u p t u o f _ k l c i c p r o f t p e c x e e t a t s w o l n i s k c o l c i c p l l a s p o t s , w o l l a n g i s n e h w ) 5 ( 4 2 , 3 22t u p t u o] 0 - 1 [ k l c u p cs t u p t u o k c o l c u p c v 5 . 2 6 21t u p t u o# d a e r p s / 0 f e r m u r t c e p s d a e r p s n o - r e w o p d n a t u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 v 3 . 3 n o i t p o p a r t s e l b a n e 5 , 3 () e l b a n e g n i k c o l c m u r t c e p s d a e r p s = w o l p a r t s e l b a s i d g n i k c o l c m u r t c e p s d a e r p s = h g i h p a r t s 7 21t u p t u o# 8 4 l e s / 1 f e r z h m 4 2 / 8 4 n o - r e w o p d n a t u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 v 3 . 3 5 , 4 n o i t p o p a r t s t c e l e s w o l d e p a r t s n e h w z h m 8 4 = t u p t u o 4 1 n i p h g i h d e p p a r t s n e h w z h m 4 2 = t u p t u o 4 1 n i p 8 2 , 9 1 , 2 1 , 81r e w o pv d d r e w o p v 3 . 3 1 2 , 5 1 , 7 , 1r e w o pv s s d n u o r g v 3 . 3 5 21r e w o pv 2 d d r e w o p v 5 . 2 2 21r e w o pv 2 s s d n u o r g v 5 . 2
224 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8315-2 04/08/99 pi6c103 precision clock synthesizer for mobile pcs # 6 6 / 0 0 1 l e s] 1 : 0 [ k l c u p c 0z h m 6 6 1z h m 0 0 1 select functions clock enable configuration # p o t s _ u p c# p o t s _ i c p# n w d _ r w p k l c u p c ] 1 : 0 [ k l c i c p ] 5 : 1 [ f _ k l c i c p r e h t o s k c o l c l a t s y r cs ' o c vz h m 8 4 xx 0 w o lw o lw o ld e p p o t sf f of f of f o 00 1w o lw o lz h m 3 3g n i n n u rg n i n n u rg n i n n u rg n i n n u r 011w o lz h m 3 3z h m 3 3g n i n n u rg n i n n u rg n i n n u rg n i n n u r 10 1 z h m 6 6 / 0 0 1w o lz h m 3 3g n i n n u rg n i n n u rg n i n n u rg n i n n u r 111 z h m 6 6 / 0 0 1z h m 3 3z h m 3 3g n i n n u rg n i n n u rg n i n n u rg n i n n u r # s t n o i t c n u f n o i t p i r c s e d s t u p t u o u p cf _ i c p , i c pf e rm 4 2 / 8 4m 8 4 0z - i hz - i hz - i hz - i hz - i hz - i h 1l a m r o nz h m 6 6 / 0 0 1z h m 3 3z h m 8 1 3 . 4 1z h m 4 2 / 8 4z h m 8 4 function description
225 ps8315-2 04/08/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c103 precision clock synthesizer for mobile pcs cpuclk (internal) cpuclk (internal) pciclk_f (free-running) cpu_stop# pci_stop# pwr_dwn# cpuclk (external) cpu_stop# is an input signal used to turn off the cpu clocks for low power operation. cpu_stop# is asserted asynchronously by the external clock control logic with the rising edge of free running pci clock and is internally synchronized to the extern al pciclk_foutput. all other clocks continue to run while the cpu clocks are disabled. the cpu clocks are always stopped in a low state and started guaranteeing that the high pulse width is a full pulse. cpu clock on latency is 2 or 3 cpu clocks and cpu clo ck off latency is 2 or 3 cpu clocks. cpu_stop# timing diagram notes: 1. all timing is referenced to the cpuclk. 2. the internal label means inside the chip and is a reference only. this in fact may not be the way that the control is designed. 3 cpu_stop# is an input signal that must be made synchronous to the free running pci_f. 4. on/off latency shown in the diagram is 2 cpu clocks. 5. all other clocks continue to run undisturbed. 6. pwr_dwn# , pci_stop# are shown in a high state. 7. diagrams shown with respect to 66 mhz. similar operation as cpu = 100 mhz. power management timing notes: 1. clock on/off latency is defined as the number of rising edges of free running pciclks between when the clock disable goes low/high to when the first valid clock comes out of the device. 2. power-up latency is from when pwr_dwn# goes inactive (high) to when the first valid clocks are driven from the device. l a n g i se t a t s l a n g i s y c n e t a l k l c i c p g n i n n u r e e r f f o s e g d e g n i s i r f o . o n # p o t s _ u p c) d e l b a s i d ( 01 ) d e l b a n e ( 11 # p o t s _ i c p) d e l b a s i d ( 01 ) d e l b a n e ( 11 # n w d _ r w p) n o i t a r e p o l a m r o n ( 1s m 3 ) n w o d r e w o p ( 0. x a m 2
226 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8315-2 04/08/99 pi6c103 precision clock synthesizer for mobile pcs notes: 1. all timing is referenced to the cpuclk. 2. pci_stop# signal is an input signal which must be made synchronous to pci_f output. 3 internal means inside the chip. 4. all other clocks continiue to run undisturbed. 5. pwr_dwn# cpu_stop# are shown in a high state. 6. diagrams shown with respect to 66 mhz. similar operation as cpu = 100 mhz. pci_stop# is an input signal used to turn off pci clocks for low power operation. pci clocks are stopped in the low state and started pci_stop# timing diagram notes: 1. all timing is referenced to the cpuclk. 2. the internal label means inside the chip and is a reference only. 3. pwr_dwn# is an asynchronous input and metastable conditions could exist. the signal is synchronized inside the part. 4. the shaded sections on the vco and the crystal signals indicate an active clock. 5. diagrams shown wth respect to 66 mhz. similar operations as cpu = 100 mhz. pwr_dwn# timing diagram the pwr_dwn# is used to place the device in a very low power state. pwr_dwn# is an asynchronous active low input. internal clocks are stopped after the device is put in power-down mode. cpuclk (internal) pciclk (internal) pciclk_f (free-running) cpu_stop# pci_stop# pwr_dwn# pciclk (external) cpuclk (internal) pciclk (internal) vco pwr_dwn# cpuclk (external) pciclk (external) crystal with a guaranteed full high pulse width. there is only one rising edge of external pciclk after the clock control logic. the power-on latency is less than 3ms. pci_stop# and cpu_stop# are ?don?t cares? during the power-down operations. the ref clock is stopped in the low state as soon as possible.
227 ps8315-2 04/08/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c103 precision clock synthesizer for mobile pcs storage temperature ............................................................ ?65c to +150c ambient temperature with power applied ............................. ?0c to +70c 3.3v supply voltage to ground potential ............................. ?0.5v to +4.6v 2.5v supply voltage to ground potential ............................. ?0.5v to +3.6v dc input voltage ................................................................... ?0.5v to +4.6v dc electrical characteristics (v ddq3 = +3.3v 5%, v ddq2 = +2.5v 5%, t a = 0c to +70c) 6 1 - 2 0 1 c 6 i p n o i t i d n o c n o i t p m u s n o c y l p p u s v 5 . 2 . x a m , s d a o l p a c e t e r c s i d . x a m v 2 q d d v 5 2 6 . 2 = v = s t u p n i c i t a t s l l a 3 q d d v r o s s n o i t p m u s n o c y l p p u s v 3 . 3 . x a m , s d a o l p a c e t e r c s i d . x a m v 3 q d d v 5 6 4 . 3 = v = s t u p n i c i t a t s l l a 3 q d d v r o s s e d o m n w o d r e w o p ) 0 = # n w d r w p ( 0 0 1 m a0 0 5 m a z h m 6 6 e v i t c a 0 = # 6 6 / 0 0 1 l e s a m 2 7a m 0 7 1 z h m 0 0 1 e v i t c a 1 = # 6 6 / 0 0 1 l e s a m 0 0 1a m 0 7 1 maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
228 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8315-2 04/08/99 pi6c103 precision clock synthesizer for mobile pcs dc operating specifications l o b m y ss r e t e m a r a ps n o i t i d n o c. n i m. x a ms t i n u v d d % 5 v 3 . 3 = v h i e g a t l o v h g i h t u p n iv d d 0 . 2v d d 3 . 0 + v v l i e g a t l o v w o l t u p n iv s s 3 . 0 -8 . 0 i l i t n e r r u c e g a k a e l t u p n iv < 0 n i v < d d 5 -5 + v d d 5 . 2 =% 5 v v h o e g a t l o v h g i h t u p t u oi h o a m 1 - =0 . 2 v v l o e g a t l o v w o l t u p t u oi l o a m 1 =4 . 0 v d d % 5 v 3 . 3 = v h o e g a t l o v h g i h t u p t u oi h o a m 1 - =0 . 2 v v l o e g a t l o v w o l t u p t u oi l o a m 1 =4 . 0 v d d 3 . 3 =% 5 v v h o p e g a t l o v h g i h t u p t u o s u b i c pi h o a m 1 - =4 . 2 v v l o p e g a t l o v w o l t u p t u o s u b i c pi l o a m 1 =5 5 . 0 c n i e c n a t i c a p a c n i p t u p n i5 f p c l a t x e c n a t i c a p a c s n i p l a t x0 . 3 15 . 2 2 c t u o e c n a t i c a p a c n i p t u p t u o6 l n i p e c n a t c u d n i n i p7h n t a e r u t a r e p m e t t n e i b m aw o l f r i a o n00 7c
229 ps8315-2 04/08/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c103 precision clock synthesizer for mobile pcs type 1: cpu clock buffers (2.5v) l o b m y ss r e t e m a r a ps n o i t i d n o c. n i m. p y t. x a ms t i n u i n i m h o t n e r r u c p u - l l u pv t u o v 0 . 1 =8 7 - a m i x a m h o t n e r r u c p u - l l u pv t u o v 5 7 3 . 2 =7 6 - i n i m l o t n e r r u c n w o d - l l u pv t u o v 2 . 1 =1 8 i x a m l o t n e r r u c n w o d - l l u pv t u o v 3 . 0 =0 6 t h r e t a r e g d e e s i r t u p t u o 1 e p y t v 5 . 2v 0 . 2 - v 4 . 0 @ % 5 v 5 . 214 s n / v t h f e t a r e g d e l l a f t u p t u o 1 e p y t v 5 . 2v 4 . 0 - v 0 . 2 @ % 5 v 5 . 214 type 3: ref buffers (3.3v) buffer specifications e m a n r e f f u bv d d ) v ( e g n a r( e c n a d e p m i w )e p y t r e f f u b u p c5 2 6 . 2 - 5 7 3 . 23 . 7 1 ~ 8 . 61 e p y t z h m 4 2 / 8 4 , f e r5 6 4 . 3 - 5 3 1 . 30 6 - 0 23 e p y t f e r / i c p5 6 4 . 3 - 5 3 1 . 35 5 - 2 15 e p y t type 5: pci clock buffers (3.3v) l o b m y ss r e t e m a r a ps n o i t i d n o c. n i m. p y t. x a ms t i n u i n i m h o t n e r r u c p u - l l u pv t u o v 0 . 1 =9 2 - a m i x a m h o t n e r r u c p u - l l u pv t u o v 5 7 3 . 2 =3 2 - i n i m l o t n e r r u c n w o d - l l u pv t u o v 2 . 1 =9 2 i x a m l o t n e r r u c n w o d - l l u pv t u o v 3 . 0 =7 2 t h r e t a r e g d e e s i r t u p t u o 3 e p y t v 3 . 3v 4 . 2 - v 4 . 0 @ % 5 v 3 . 35 . 02 s n / v t h f e t a r e g d e l l a f t u p t u o 3 e p y t v 3 . 3v 4 . 0 - v 4 . 2 @ % 5 v 3 . 35 . 02 l o b m y ss r e t e m a r a ps n o i t i d n o c. n i m. p y t. x a ms t i n u i n i m h o t n e r r u c p u - l l u pv t u o v 0 . 1 =3 3 - a m i x a m h o t n e r r u c p u - l l u pv t u o v 5 3 1 . 3 =3 3 - i n i m l o t n e r r u c n w o d - l l u pv t u o v 5 9 . 1 =0 3 i x a m l o t n e r r u c n w o d - l l u pv t u o v 4 . 0 =8 3 t h r e t a r e g d e e s i r t u p t u o 5 e p y t v 3 . 3v 4 . 2 - v 4 . 0 @ % 5 v 3 . 314 s n / v t h f e t a r e g d e l l a f t u p t u o 5 e p y t v 3 . 3v 4 . 0 - v 4 . 2 @ % 5 v 3 . 314
230 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8315-2 04/08/99 pi6c103 precision clock synthesizer for mobile pcs ac timing k c o l c t s o h . 1 e r u g i f t e s f f o k l c i c p o t s r e t e m a r a p z h m 6 6z h m 0 0 1 s t i n u . n i m. x a m. n i m. x a m t p k h ) v 5 . 2 (d o i r e p k l c t s o h0 . 5 15 . 5 10 . 0 15 . 0 1 s n t h k h ) v 5 . 2 (e m i t h g i h k l c t s o h2 . 50 . 3 t l k h ) v 5 . 2 (e m i t w o l k l c t s o h0 . 58 . 2 t e s i r h ) v 5 . 2 (e m i t e s i r k l c t s o h4 . 06 . 14 . 06 . 1 t l l a f h ) v 5 . 2 (e m i t l l a f k l c t s o h4 . 06 . 14 . 06 . 1 t r e t t i j ) v 5 . 2 (r e t t i j k l c t s o h0 5 20 5 2s p ) v 5 . 2 ( e l c y c y t u dv 5 2 . 1 t a d e r u s a e m5 45 55 45 5% t w k s h ) v 5 . 2 (w e k s k l c s u b t s o h5 7 15 7 1s p t l z p t , h z p y a l e d e l b a n e t u p t u o0 . 10 . 80 . 10 . 8 s n t z l p t , z h p y a l e d e l b a s i d t u p t u o0 . 10 . 80 . 10 . 8 t b t s h p u - r e w o p m o r f n o i t a z i l i b a t s k l c t s o h33s m t p k p d o i r e p k l c i c p0 . 0 3 0 . 0 3 s n t s p k p y t i l i b a t s d o i r e p k l c i c p0 0 50 0 5s p t h k p e m i t h g i h k l c i c p0 . 2 10 . 2 1 s n t l k p e m i t w o l k l c i c p0 . 2 10 . 2 1 t w k s p w e k s k l c s u b i c p0 0 50 0 5s p t t e s f f o p h t e s f f o k c o l c i c p o t t s o h5 . 10 . 45 . 10 . 4s n t b t s p p u - r e w o p m o r f n o i t a z i l i b a t s k l c i c p33s m
231 ps8315-2 04/08/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c103 precision clock synthesizer for mobile pcs output buffer test point 2.0 1.25 0.4 thkh duty cycle thkp 2.5v clocking interface thkl t hfall t hrise 2.4 1.5 0.4 tpkh tpkp 3.3v clocking interface (ttl) tpkl t pfall t prise test load figure 2. clock output waveforms figure 1. host clock and pci clk timing 1.25v 2.5v t hpoffset host clk pci clk v ss 1.5v 3.3v v ss t hpoffset 1.25v 2.5v host clk v ss t hskw pci clk 1.5v 3.3v v ss t pskw 1.5v 1.25v 1.25v
232 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ps8315-2 04/08/99 pi6c103 precision clock synthesizer for mobile pcs pcb layout suggestion note: this is only a suggested layout. there may be alternate solutions depending on actual pcb design and layout. as a general rule, c2-c6 should be placed as close as possible to their respective v dd . recommended capacitor values: c2-c6 ............... 0.1 m f, ceramic c1, c7 ............ 22 m f c2 c3 c6 c5 c4 fb2 vcc c7 22 m f via to vdd plane via to gnd plane void in power plane 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vss vdd vdd vdd vss vss vdd vss vdd fb1 vcc c1 22 m f
233 ps8315-2 04/08/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c103 precision clock synthesizer for mobile pcs cpuclk pciclk ref 2 6 cl cl cl pi6c103 1 device load meets pci2.1 req. 1 device load 2 pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com ordering information n / pn o i t p i r c s e d h 3 0 1 c 6 i pe g a k c a p p o s s n i p - 8 2 l x x - 3 0 1 c 6 i pe g a k c a p p o s s t n i p - 8 2 k c o l cd a o l . n i md a o l . x a ms t i n us e t o n ) k l c h ( s k c o l c u p c0 10 2 f p s d a o l 2 e l b i s s o p , d a o l e c i v e d 1 ) k l c p ( s k c o l c i c p0 30 3s t n e m e r i u q e r 1 . 2 i c p s t e e m z h m 8 4 , f e r0 10 2d a o l e c i v e d 1 minimum and maximum expected capacitive loads notes: 1. maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer. 2. minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer. 3. rise/fall times are specified with pure capacitive load as shown. testing is done with an additional 500 w resistor in parallel. design guidelines to reduce emi 1. place series resistors and ci capacitors as close as possible to the respective clock pins. typical value for ci is 10pf. series resistor value can be increased to reduce emi provided that the rise and fall time are still within the specified values. 2. minimize the number of ?vias? of the clock traces. 3. route clock traces over a continuous ground plane or over a continuous power plane. avoid routing clock traces from plane to plane (refer to rule #2). 4. position clock signals away from signals that go to any cables or any external connectors.

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